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A software DDS for producing the
10MHz reference signal for 2.5GHz PLL
1. The principle:
The software DDS running
on a AT90S1200 is producing a 39kHz signal that can be adjusted in very
fine steps. A 10MHz VCXO (voltage controlled crystal oscillator) signal
is divided by 256 (10MHZ:256=39kHz) and phase locked to the DDS signal.
The loop bandwidth of the PLL loop is very small (around 100Hz) so there
are no DDS spurious components on the 10MHz signal. The pulling range of the VCXO
is around 100ppm, giving a pulling range of 100kHz if the reference is
used for a 1GHz PLL.
2. The implementation:
The hardware for the DDS
is a AT90S1200 running on +5Volts supply voltage and being clocked by a
temperature compensated 13MHz crystal oscillator. (Yes I know, the AT90S1200
is only specified up to 12MHz, believe me the 8% higher clock rate is no
problem at all.) The VCXO is a standard Clapp transistor oscillator with
a normal 10MHz crystal. To make the crystal oscillator a VCXO I have put
2 varactor diodes (SMV1253) between the crystal and ground. A chip inductor
in series to the crystal brought the frequency back to 10.000MHz so I can
now tune from 10.000 to 10.001 MHz.
3. The software
The software is written
in assembler of course since every clock cycle is important for this application.
The desired frequency is set via a 3wire-bus from the main CPU in my generator.
Normally the DDS is running at full speed without even checking the input
bus. If the main CPU wants to set a new frequency it triggers an external
interrupt which stops the DDS work. In the interrupt service routine the
DDS-software reads 3 bytes via the 3wire-bus, then it resumes the DDS work.
I suggest you simply have a look on the source code. If you have questions
just don't hesitate to contact me by email and I will be glad to advise you.